1. Field of the Invention
The present invention relates to a power-up detection apparatus for detecting a time when a power voltage is over a predetermined voltage level, and more specifically, to a power-up detection apparatus configured to perform a stable operation without being affected by power noise.
2. Description of the Related Art
Generally, a power-up detection apparatus initializes a semiconductor device when an externally applied power voltage reaches a predetermined potential. Thereafter, a semiconductor device performs a normal operation when the power voltage is over the predetermined potential.
FIG. 1 shows a circuit diagram of a conventional power-up detection apparatus.
The conventional power-up detection apparatus comprises a voltage divider 1, a potential detector 2, an inverter INV1, and a buffer 3. The voltage divider 1 divides a power voltage VCC in a predetermined ratio. The potential detector 2 compares a predetermined potential with a potential N0 outputted from the voltage divider 1, and then outputs a comparison result N1. The inverter INV1 inverts the potential N1 detected by the potential detector 2. The buffer 3 buffers an output signal N2 of the inverter INV1 to output a power-up signal PWR.
The voltage divider 1 includes resistors R1 and R2 connected in series between the power voltage VCC and a ground voltage. The divided potential N0 is outputted from a common node of the resistors R1 and R2.
The potential detector 2 includes a resistor R3 and a NMOS transistor NM1. The resistor R3 is connected in series between the power voltage VCC and the ground voltage. The NMOS transistor NM1 has a gate to receive the potential N0 divided by the voltage divider 1. The potential N1 is outputted from a node where the resistor R3 is connected in common to a drain of the NMOS transistor NM1.
The buffer 3 includes inverters INV2 and INV3 for sequentially inverting an output signal N2 from the inverter INV1.
The operation of the conventional power-up detection apparatus is described below.
The power-up detection apparatus detects a potential of an external power voltage VCC, and then generates a power-up signal PWR when the power voltage VCC reaches a predetermined potential.
Here, the power-up signal precharges a predetermined node or circuit to a high or low state for initialization of a chip, that is, for stabilization of an internal power source, until the internal power reaches a predetermined potential.
However, as shown in FIG. 2, if the external power voltage VCC accompanies ripple noise, the state of the power-up signal PWR toggles whenever the power voltage VCC reaches a predetermined potential. As a result, current consumption increases, and mis-operations may occur frequently.
Specifically, as an operation power voltage is lowered, the gap between the operation power potential level and the power potential level where the power-up signal is generated decreases. Accordingly, when noise is generated in the power potential, an undesired power-up signal can be generated, thereby initializing a semiconductor device.